1. Field of the Invention
The present invention relates to a hotplug tolerant I/O circuit suitable for a device receiving a signal with a voltage higher than its supply voltage, and more particularly to the hotplug tolerant I/O circuit enabling the device to be hotplugged to a cable transmitting such a signal. Here, the term "hotplug" refers to externally connecting to the device a data signal having a voltage higher than the supply voltage of the device under the condition in which the supply voltage is not supplied to the device.
2. Description of Related Art
Conventionally, such devices that are supplied with a data signal of a voltage higher than their power supply voltage VDD have been widely used. Even when the data signal with a voltage higher than the power supply voltage VDD is supplied from the outside to the devices under the condition in which the power supply voltage VDD is being supplied to the devices, these devices carry out in their I/O circuit such control that protects transistors constituting the I/O circuit from being supplied with an excessive voltage, and prevents current on a data signal cable from flowing into the power supply (VDD and GND) of the I/O circuit.
FIG. 6 is a circuit diagram showing a conventional I/O circuit in a device. In FIG. 6, the reference numeral 60 designates the I/O circuit; 61 designates an I/O transistor circuit in which three transistors MP1, MN1 and MN2 are connected in series; 62 designates a floating gate signal generator; 63 designates a floating well signal generator; and Gl-G3 designate a gate circuit.
Next, the operation of the conventional I/O circuit will be described.
The conventional I/O circuit as shown in FIG. 6 is incorporated in a device, and functions as an I/O interface. The I/O circuit is connected to a signal cable of an external device via I/O pins under the condition in which the power supply voltage VDD is being supplied.
In this case, because the power supply voltage VDD is being applied, the I/O transistor circuit 61 is not supplied with an excessive voltage. Thus, the transistors in the I/O transistor circuit 61 are protected from damage, and no current will flow from the data signal cable to the power supply (VDD and GND) of the I/O circuit.
The conventional I/O circuit with the foregoing configuration has the following problems. First, when the signal with the voltage higher than the power supply voltage VDD is supplied from the external device to the device via the signal cable and I/O pins under the condition in which the power supply voltage VDD is not applied to the device, the transistors MP1, MN1 and MN2 constituting the I/O transistor circuit 61 are supplied with an excessive voltage, and are destroyed. This will disable the I/O circuit, and have an adverse effect on the data on the signal cable because of a current flowing from the signal cable to the power supply (VDD and GND) of the I/O circuit.